The specialist in embedded services and products ARIES will present its brand-new System-on-Module (SoM) M100PFS at Embedded World 2020 (February 25 to 27, 2020 in Nuremberg. Stand 441 – hall 3A). The M100PFS SoM is based on the PolarFire® SoC, the System-on-Chip (SoC) FPGA family from Microchip that combines a high-performance 64-bit RISC-V multicore processor subsystem with low-power FPGA technology.
“Our new platform enables customers to easily take advantage of the PolarFire SoC’s hardened real-time, Linux capable, RISC-V processor subsystem integrated with the PolarFire FPGA family, the industry’s lowest-power, mid-range FPGAs,” stated Andreas Widder, Managing Director of ARIES Embedded. “Applications can benefit from the low power consumption, thermal efficiency, and defense-grade security for a range of embedded systems that require deterministic operation.”
The new M100PFS FPGA SoM is suitable for secure, power-efficient computation in a wide range of applications including Smart Embedded Vision, Industrial Automation, Communications, and Industrial Internet of Things.
Low Power and secure
The 74 by 42 mm small M100PFS SoM runs with low device static power, low inrush current and low-power transceivers. The PolarFire FPGA technology stands out for its reliability with single-event upset (SEU) immunity, built-in SECDED and LSRAM memory interleaving built into the FPGA fabric. In addition, SECDED runs on all processor memory resources and the system controller suspend mode serves safety-critical designs. Several features support security aspects: for example, Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bit stream protection, integrated dual physically unclonable function (PUF), and 56 KB of secure, non-volatile memory (sNVM).
Powerful and versatile
The PolarFire SoC onboard M100PFS SoM from ARIES Embedded combines a Quad 64-bit RISC-V 64GC core and a 64-bit RISC-V 64 IMAC monitor core. The SoM uses the FCVG484 package that scales from the PolarFire SoC’s 23k logic element (LE) device up to the 250k LE device. A SoM offering the largest 460k LE PolarFire SoC device will be offered in later versions. The RISC-V CPU micro-architecture implementation is a simple 5-stage, single issue, in-order pipeline that is immune to the Meltdown and Spectre exploits found in common out-of-order machines.
All five CPU cores are coherent, with the memory subsystem allowing a versatile mix of deterministic real-time systems and Linux in a single multi-core CPU cluster. Processor I/Os include: 2x Gigabit Ethernet, USB 2.0 OTG, 2x CAN 2.0 A and B, Execute in place Quad SPI flash controller, 5x multi-mode UARTs, 2x SPI, 2 I2C, RTC, GPIO, and 5x watchdog timers. Memory comprises 1/2/4 GByte LPDDR4 RAM dedicated to the HMS, 1/2/4 GByte LPDDR4 RAM dedicated to the FPGA, 32 Mbit NOR Flash, and 4 - 64 GByte eMMC memory. The default configuration contains Gigabit Ethernet, UART, CAN, SPI, I²C, and USB.